This invention pertains to a circuit for compensating errors in a phase-locked loop.
In video systems for processing and displaying image information, individual phase-locked loops are commonly used to keep several subsystems in a fixed phase and frequency relationship to a reference signal such as a zero crossing of the power line waveform. In some cases such as when a sequence of video images are subtracted from one another, it is necessary to keep all subsystems in perfect synchronism so the picture elements (pixels) in all images will be exactly coincident with each other, in which case no artifacts in the difference image would result. However, in systems that require high phase and frequency stability between subsystems and that use phase-locked loops, periodic phase errors can occur. It has been discovered that these errors are due to timing errors in the power line frequency itself. Until the invention described herein was made, no one seemed to account for the fact that zero crossings of the power line frequency sometimes shifted by significant amounts before or after the zero crossing that was assumed to occur at exactly one-sixtieth or one-fiftieth of a second intervals. These phase errors occur even though all electric power generating stations in a country are synchronized by a master clock which detects and makes corrections for the errors periodically. It has been observed that if a heavy electric load has been connected to or disconnected from a power system at an unknown place in a given locale, phase errors frequently result. These errors do not affect ordinary television systems nor other communication systems adversely since in them usually a sequence of electrical actions follow occurrence of a zero crossing in a fixed time relationship and it does not make any difference when the crossing occurs since the transmitters and receivers will be similarly affected. However, in phase-locked systems where perfect coincidence of pixels between successive images is absolutely necessary, for example, the phase-locked loops cannot respond fast enough to correct for the power line phase error and temporary loss of the proper timing relationships between subsystems results.
One example, used to illustrate the new power line phase error correcting system constituting the present invention is where graphics must be written on a cathode ray tube (CRT) screen or monitor on which image data is also being written and displayed simultaneously. Here coincidence of corresponding pixels in successive images is an absolute requirement. In an effort to insure coincidence, the video camera system timing was based on the stable frequency of a crystal-controlled oscillator. This assured that the time intervals between every horizontal raster line were the same since the frequency precision of the crystal-controlled oscillator is better than the power line synchronized oscillator. In other words, in this case, the sequence of horizontal raster lines was initiated by occurrence of a power line zero crossing but from that time on the horizontal synchronizing (sync) and blanking pulses were governed by the crystal oscillator so the only effect of a zero crossing error was that the vertical scan would be terminated slightly early or slightly late so that the zero crossing reset signal might occur before or after the last intended horizontal raster line was complete. In this system, a digital video processor (DVP) processes the digitized video signals. The DVP employs a phase-locked loop to maintain synchronism with the camera and is controlled by horizontal and vertical sync signals derived from the video camera under crystal control. Thus, it would maintain phase and frequency relationship with the camera very well. However, in the same system there is a graphics display subsystem for displaying dot-matrix graphics on the CRT screen concurrently with image data. The graphics display was also locked by means of a phase-locked loop to the video camera and the input frequency to this loop is the horizontal blanking pulse frequency. Before the present invention was employed, when a power line phase error occurred, the phase-locked loop sensed it as an error in its own frequency and tried to correct it, which resulted in the graphics becoming distorted and torn at the top of the raster. The present invention overcomes this problem in the described illustrative system but is applicable to a variety of systems wherein instantaneous phase correction in a phase-locked loop is necessary.